Adding an effective package to the design cycle can pinpoint areas critical to EMC compliance
Dirk Müller, FlowCAD, Munich, GERMANY
Ultimately, electromagnetic compatibility can be validated only in the measurement chamber with existing prototypes. Those tests are time consuming and expensive. There are various ideas for cutting the costs of testing with early software simulations during the design process. Still, EMC is complex discipline and carrying out a complete 3D simulation for an entire complex board, in an acceptable timeframe, is presently very difficult. Because of this difficulty, experts concentrate on simulating only critical areas of the board, such as power and ground systems or single critical nets to determine the cause of radiation (emission) and irradiation (susceptibility).The knowledge gained from those analyses finds its way into design rules given to PCB designers.With a recently developed simulation software package, the user can view completely routed layout designs from most popular PCB layout tools. During a layout review, various design rules for all layers, nets, or traces are checked. Imports of layout data of the following PCB layout tool suppliers are available: Altium, Cadence, Mentor, OrCAD and Zuken. This package was developed jointly by experts from a simulation software company and a well know IT industry giant. One contributed knowledge for interfacing with the various PCB layout tools while the latter drew on decades of expertise in creating and verifying EMC/SI rules. Over the years, company experts had examined EMC issues using sophisticated measurement techniques on a variety of designs, eventually creating general valid design rules. Critical designs were checked against those design rules, and the results were thoroughly verified by measurements. The final product of this collaboration was a software tool that recognizes the main contributors to frequent electromagnetic perturbations. This general purpose software does not require an expert on EMC. It puts the PCB designer in a position to check his designs for EMC compliance. In turn, the design staff member doing the layout is provided a list with a detailed description and a possible scenario for fixing any EM problem. The integrated viewer shows the exact location of the violation within the design. In fact, a major focus in developing this package was to give users without specialized knowledge the ability to locate EMC violations easily and early in the design cycle, thus minimizing costly measurements and redesigns.Rule based checks
Emission or coupling is caused by violations of certain geometrical rules. For example, consider the return current path of the design. Each signal has a path preset by the signal traces, but there is always a return path—often on power and ground layers. The return current always prefers the route of least resistance; and at higher frequencies, this will be the route of lowest impedance. The new software determines where the return path is discontinued. For example, the path might stop because of a split plane. If the return path cannot follow the signal path geometrically, the return current will use a different path. Depending on the size of the area surrounding the detour of the return current, an antenna may occur radiating or receiving interference, resulting in failure to achieve EMC compliance or possible design malfunctions. This software tool recognizes if such discontinuities of copper areas at power supply layers are connected by one or more capacitors for high frequencies (Figure 1). Those capacitors will create a path with low impedances for the return current, avoiding undesirable return paths.Figure 1. An EMC error caused by a capacitor that is too far away from the signal to bridge the split plane.Another rule searches for nets that change signal layer and reference plane for the return current. Little radiation occurs if the signal traces change only from above the reference plane to directly below it. In this case, the return current could continue to flow in the same plane. If signal layers and the reference plane change simultaneously, the return current paths must be secured (Figure 2). With capacitors close to the via, one must avoid the return currents that create unwanted routes and result in a loop. This software design rule must recognize and allow for a layer change in the area of escape-vias below a BGA because the return current does not flow via the capacitor but through the BGA. If this rule is violated, the via where changing layers occurred will be highlighted by the software.Figure 2. If signal layers and the reference plane change simultaneously, the return current paths needs to be secured. At higher signal frequencies, one needs to reduce the length of the line at the outer layers. The maximum allowed line length will be checked and violations will be indicatedAnother rule will check for maximum distance of a blocking capacitor to a connector pin on the power supply voltage. Because a blocking capacitor has a small effective radius, a permissible distance to the decoupling pin cannot be exceeded. Otherwise, the capacitor is useless and should be omitted. Violation of this rule will be listed along with the distance to the respective capacitor. A final important rule is that a trace should not be routed too closely to the edge of its reference plane. In this case, the line impedance will change and may result in signal reflections at the impedance discontinuities.With this software package, the user can check specific rules, be guided through an error list, and then be shown the critical areas in the layout. Changing the position of the components early in the design phase can create layout routes that forestall EMC problems. Supplementary shielding or filters might not be needed, saving valuable board space and component costs. Conclusion
As board design becomes ever more complex and EMC regulations grow ever more stringent, seeking solutions early in the design cycle has become a necessity. Software simulation packages, especially when combined with effective interfaces with widely used layout tools. can prove invaluable in the process of product development.Dirk Müller received his electronic engineering degree in 1989. Since 2003 Mueller has been Managing Director of FlowCAD, the Cadence Channel Partner for PCB products in Central Europe as well as other flow integrated vendors like SimLab, Mecadtron and Valor.