Sassan Tabatabaei, SiTime Corporation
Electronic devices have to operate in close proximity, whether it is in the home, office, industrial establishment, or outdoors. Each of the devices may radiate electromagnetic energy, which can interfere with the operation of the rest of the devices. To avoid such harmful interference, governments and industry bodies limit the amount of energy that any device can radiate. Environmental compliance standards such as FCC Class A and B specify these limits for different categories of equipment, based on the location of end use.
One of the key sources of electromagnetic interference (EMI) energy is the clock tree. Good design and layout of the clock tree ensures that the system not only performs well without major timing issues, but also ensures the system passes environmental compliance standards. Careful consideration must be given to the following:
The clock source and associated traces
The circuits that are the driven with the clock. These circuits may consist of a number of discrete devices, but more often than not, it includes a small number of large integrated circuits (ICs) that perform most of the key functions for that application.
The I/O circuitry and traces that exchange data from one IC to another or to external systems.
Each trace (clock or data) can be considered a transmission line and different kinds of traces have varying characteristics. Transmission line theory is well-established in the electronics industry, so we will not go into that detail in this paper.
The main reason for EMI radiation is lack of signal return path in transmission lines. This typically occurs when there is a discontinuity in the ground or signal return plane underneath the clock and signal traces. The EMI energy is typically concentrated at the clock frequency and its harmonics. The energy at higher harmonics depends on the clock signal shape. Because most clock signals have near square-wave shape with finite slew rate, the harmonics of the signal do play an important role in EMI. Generally, faster slew rates and overshoots/undershoots due to inadequate termination result in larger EMI at the frequencies of the harmonics.
The main EMI reduction techniques are as follows:
2. Using solid ground or signal return path for high-speed signals
3. Signal filtering
4. Reducing rise/fall time
5. Using spread-spectrum clocking (SSC) modulation
Shielding requires enclosing the system in a grounded conductive box to block the radiation of energy to the outside. In many consumer and computing applications, such enclosures are costly or are impractical due to the physical constraint of the system. The use of a solid ground is a recommended design practice for not only reducing EMI, but also for maintaining good signal integrity in high-speed signal paths. However, small amounts of energy will radiate even in the presence of a solid ground from the top side of the trace. In some high density boards, it may be difficult to guarantee a solid ground or return path for all signals without adding extra ground layers, which increases the board cost.
The following sections discuss the remaining three techniques in greater detail.
II. SIGNAL FILTERING FOR EMI REDUCTION
EMI may radiate from the signal output pins and traces. Typically, much of such radiation is from the board traces because the board traces are longer than the clock device pins or internal IC traces. In some cases, the short traces in the large IC packages can dominate the EMI at relatively high frequencies (greater than 500 MHz).
Using low pass filters at the high-speed clock and data outputs effectively attenuates the signal frequency content, especially at high harmonics. Typically, simple RC-based low pass filters are used due to their simplicity, low cost, and small board space requirement. A RC filter is a single pole filter with 3dB attenuation at its cutoff frequency and 20dB/dec attenuation for frequencies above that. The cutoff frequency has to be approximately twice that of the clock frequency to avoid reducing the signal swing too much; otherwise the signal swing may violate the logic threshold of the receiver digital circuits. This filter is suitable for reducing EMI at high harmonics; for example, it provides 20dB attenuation at the 11th harmonic of a clock signal. It is possible to design more complex filters, such as second order ones to attenuate higher harmonics even more, but they are more bulky and expensive.
Filtering technique has the following disadvantages:
1. The board designer has to place the filters at the dominant EMI signal outputs, but it is often difficult to identify those signals. In designs where one clock source is driving one or two main ICs, placing the filter on the clock signal may be effective solutions.
2. Low pass filters do not offer much EMI reduction at the main clock frequency and first two or three harmonics.
3. The filters present resistive and capacitive load to the output drivers, which in turn increase the power consumption. The resistive current can be estimated by dividing the signal DC level by the equivalent resistor at the output. The capacitive current is computed as CVF, where C is the equivalent capacitance at the output, V is the voltage swing, and F is the clock frequency.
4. The RC filters take board space and increase the cost. This is especially true if separate filters have to be used for multiple signals traces.
III. EMI REDUCTION THROUGH RISE/FALL TIME CONTROL
Reducing rise/fall time for single-ended clocks and signals is an effective way of reducing harmonic EMI. Figure 1 shows the amplitude of clock harmonics as a function of rise/fall time (rise and fall times are assumed to be the same). All the rise times are selected to maintain the peak-to-peak clock signal to its maximum value. As this figure shows, most harmonics can be reduced by 20dB or greater while maintaining the peak-to-peak clock swing. As such, the rise/fall time reduction provides better harmonic EMI reduction than RC filters without sacrificing the voltage swing.
Most single-ended drivers, such as LVCMOS, consist of push-pull circuits. In such circuits, the maximum drive capability of the driver and the effective load capacitance define the rise/fall time. Therefore, there are two ways to increase the rise/fall time:
Increase the load capacitance. This method has the disadvantage of increasing current consumption.
Decrease the output current drive. This method does not increase the current consumption, but requires the clock device output drive strength to be programmable.
Some clock devices and output buffers in the large ICs allow drive strength adjustment. Examples include programmable oscillators.
The main disadvantages of this EMI reduction method are:
It only reduces clock harmonic EMI, and
It may not be possible to reduce the rise/fall time sufficiently for high-speed clocks and signals.
Figure 1. Clock signal harmonic amplitude decreases as the rise/fall time increases. Rise times are normalized to the clock period.
IV. EMI REDUCTION USING SPREAD-SPECTRUM CLOCKING (SSC)
Waveform shaping methods, such as filtering and rise/fall control are ineffective for reducing the EMI generated at the main harmonic from the clock traces. Additionally, they do not decrease EMI from the chipsets and traces that are driven by buffers without filters or rise/fall time adjustment. In addition to the clock traces, the data lines may also radiate energy. Such energy is attenuated by the random nature of the data signals, but it may still exceed acceptable levels because there are typically many more data signals in a system than clock ones.
Board designers use slew rate control and proper transmission line design to reduce EMI, but due to large number of sources, the residual EMI at main frequency and its harmonics may still be high. In such cases, spread spectrum clocking is an effective system-wide EMI reduction solution.
SSC is implemented by modulating the clock signal with a low rate frequency modulation. The modulation spreads the clock energy over a larger bandwidth, which reduces the maximum power for a given spectral bandwidth. The most common spectral bandwidth for measuring the peak EMI is 100 kHz, as defined by the federal communication commission (FCC). The SSC modulation rate in most applications is 32 kHz to provide fairly flat response in the region over which the carrier frequency is spread.
The most commonly used modulation profiles is the triangular one, as shown in Figure 2b. This profile effectively distributes the carrier frequency energy uniformly over the modulation range and provides a fairly flat spectrum at the clock frequency and its harmonics. Sinusoidal modulation does not provide the same flatness due to its non-uniform frequency distribution. Figure 2c shows Hershey-Kiss shaped modulation profile, which offers optimally flat carrier spectrum. This profile offers 1.5dB less peak EMI than triangular modulation, but it is more complex to implement.
Assuming that the clock frequency is modulated by a given percentage, SSCpercentage, and that the percentage harmonic spectrum is fairly flat after SSC nodulation, the peak energy reduction can be approximated as below:
where, ASSC(i) is the amplitude of the clock i-th harmonic amplitude after SSC modulation, fSSC _range is the frequency range that the clock harmonic spreads over after SSC modulation, Aclk (i) is the clock i-th harmonic amplitude before SSC modulation, and RBW is the bandwidth for measuring EMI energy. The fSSC _range is computed as fSSC _ range = fclk (i).SSCpercentage. Therefore, the EMI reduction at the i-th harmonic can be computed as below:
ASSC(i)(dB) = Aclk(i)(dB) −10log10(SSCpercentage. fclk(i)/ RBW )
This equation indicates that the larger the clock frequency, the larger the EMI reduction. Also, the EMI at the higher harmonics of the clock are reduced more than the lower ones.
Figure 2. SSC modulation profiles.
The SSC modulation profile can be centered on the non-SSC clock frequency, or be less than the non-SSC clock frequency. The former is called center-spread, and the latter down-spread. The down-spread ensures that the SSC modulation does not cause periods shorter than those of the clock without the SSC modulation. This is especially important for processor applications to ensure that that clock period does not violate the critical path timing in the internal state machines of the processor. The down-spread, however, leads to an average frequency that can vary over a large range, e.g., a few hundred parts per million (ppm). Such large average frequency variation may result in buffer overflow in some I/O systems.
The center-spread guarantees more accurate average frequency, but leads to short periods. For center-spread modulation, the user has to ensure that the processor and state machines are rated for the maximum frequency of the clock with SSC. The advantage is easier buffer management in the I/O systems.
Figure 3 and Figure 4 show the EMI reduction for the measured main harmonic of 12 MHz and 125 MHz clocks, respectively. The modulation range is 2% and modulation profile is triangular in both cases. These figures clearly show that the higher the clock frequency, the larger the EMI reduction. Figure 5 and Figure 6 show the EMI reduction for the first, third, fifth, and seventh harmonics of a 100 MHz clocks with 2% down-spread triangular modulation. They indicate that the EMI at higher harmonics are reduced more than that of lower harmonics.
Figure 3. Main harmonic spectrum for a 12 MHz clock with amd without 2% down-spread triangular SSC modulation.
Figure 4. Main harmonic spectrum for a 125 MHz clock with and without 2% down-spread triangular SSC modulation.
Figure 5. First and third harmonic spectrum for a 100 MHz clock with and without 2% downspread triangular SSC modulation.
Figure 6. Fifth and seventh harmonic spectrum for a 100 MHz clock with and without 2% downspread triangular SSC modulation.
SSC is used widely in certain applications, such as printers and microcontroller applications because it offers the following advantages:
1. Reduced cost:
a. No need to use expensive shielding techniques.
b. Recued ground layers. It may be difficult to ensure that all data and clock signals have uninterrupted ground plane underneath, which lead to EMI radiation from some traces. One solution is to add ground plane layers, but that adds board cost. SSC technique can reduce EMI and save additional ground planes.
2. Flexibility: A system may be designed with non-SSC clocks. If the EMI testing shows EMI issues, the oscillator can be replaced with SSC ones to reduce EMI without changing anything else in the system. Also, the SSC percentage may be adjusted to the minimum needed to meet EMI goals. This will minimize the impact on the system timing margins.
3. System-wide EMI reduction. Other EMI reduction approaches, such as filtering, waveform shaping, ground plane continuity, and shielding reduce EMI at the specific places where this techniques are used. In contrast, adding SSC to the clock, reduces EMI from all signals that are synchronous with that clock regardless of their locations.
SSC modulation, however, is not always a solution to EMI problems in the following situations:
1. SSC modulation increases period jitter. For example, in 100MHz clock with 1% SSC modulation, the peak-to-peak period jitter increase by 1% of the clock period, or 100ps. When center-spread is used, some periods are shorter than the ones without SSC, which may violate the critical path timing in digital circuits. To avoid this issue, down-spread is often the preferred SSC type because it guarantees that no clock period becomes shorter than the ones without SSC.
2. Deeper I/O buffers and more complex buffer management required. Many systems use two different clocks at the data source, e.g., a processor, and data sink, e.g., peripheral device. Since the clocks are not synchronous, the sink needs to buffer received data and avoid loosing data. Also, the sink has to include some type of buffer management protocol to ensure it can adjust for the rate difference between its clock and the source one. When SSC is used, the buffer depth and management protocol has to be able to accommodate significant variable difference between source and sink clock rate. For example, the sink may ignore or insert some bits between transmission packets to adjust the rate difference dynamically. The I/O standard that allow such protocols optionally include DDR2, DDR3, PCI, PCI-X, PCI-Express, Serial ATA (SATA), fully-buffered DIMM (FB-DIMM). The more recent USB3.0 standard includes SSC as a mandatory feature. Using SSC modulation for other types of I/O that do not include specific buffering features is generally not recommended.
SSC clock jitter performance is often specified using the concept of cycle-to-cycle jitter. C2C jitter is defined as the variation of one cycle of a clock signal relative to its adjacent cycle. Because the SSC modulation rate is typically very low, the impact of the SSC on two adjacent cycles is very similar, and hence their difference is very insensitive to the SSC modulation. It can be shown that the SSC-induced phase modulation is filtered with a filter response that has a 3dB corner frequency and ¼ of the clock frequency and attenuation rate of 40dB/dec at low frequency offset . This ensures that C2C capture the jitter at higher frequency offsets and excludes SSC-induced jitter. As such, it captures the impact of clock jitter in terms of critical path timing more effectively.
EMI radiation may result in significant interference of one electronic system to other systems close by. To ensure multiple systems can operate properly in close proximity, EMI radiation from each system has to meet limits defined by industry or government bodies. Major EMI reduction techniques include:
2. Signal filtering
3. Using solid ground or signal return path for high-speed signals
4. Reducing rise/fall time
5. Using spread-spectrum clocking (SSC) modulation
The shielding can be costly, and sometimes difficult to accommodate due to the physical constraints of the system. Signal filtering requires additional board space and components, and can also increase power consumption. Ensuring solid ground is an effective method, which should be followed as a good board layout design practice. However, it is not always a practical solution because it can lead to more ground plane layers, which increases cost. Rise/fall time reduction is a very effective method for reducing EMI at high harmonics without increasing power consumption or requiring additional board components. However, such method is only possible if the clock and data buffers and I/Os provide rise/fall time adjustment.
All the methods above are localized to the specific traces. In contrast, SSC modulation reduces EMI system-wide because the modulation is distributed to all the signal that stem from the SSC clock, regardless of where that are located. It also reduces EMI at both main harmonics and high harmonics. The main drawback of SSC modulation is that its use is limited to system that use I/O interfaces that include buffer management features required for handling the dynamic rate variations caused by the SSC modulation. For example, it cannot be used for Ethernet and high-speed USB2.0 I/Os.
 Office of Engineering and Technology, “Understanding the FCC regulations for low-power, non-licensed transmitters”, Federal Communication Commission, OET Bulletin, No. 63, October 1993.
 K. Harding, R. A. Oglesbee, F. Fisher, “Investigation into the interference potential of spread-spectrum clock generation to broadband digital communications”, IEEE Transaction on Electromagnetic Compatibility, Vol. 45, No. 1, February 2003.
 H. Skinner, K. Slattery, “Why spread spectrum clocking of computing devices is not cheating”, IEEE International Symposium on Electromagnetic Compatibility, 2001.
SASSAN TABATABAEI has held the position of Director of Strategic Applications at SiTime Corporation since 2008. Prior to that, he held executive and technical management positions at Guide Technology, Virage Logic, and Vector12. He received his Ph.D. from the University of British Columbia, Vancouver, BC, Canada in Electrical Engineering in 2000.