Title: High Speed Digital Seminar Tour 2016
Date: April 14 2016
Location: Chelmsford, Massachusetts, USA
Description: In digital standards, every generational change introduces new challenges and risks. In this seminar, we will share our industry expertise and discuss solutions for high-speed digital design and test to help you anticipate these challenges, reduce risks and accelerate your designs. You will learn new design and test strategies for signal integrity, USB 3.1 Tx/Rx test, Type-C Connector, PAM-4/400G, and DDR4/LPDDR4.
Who should attend:
Design engineers, signal integrity engineers, quality engineers, validation engineers, test engineers, architects, project managers, program managers, application managers, and application engineers.
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