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Interference Technology

For EMI / EMC Engineers

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High Speed Digital Seminar Tour 2016

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Title: High Speed Digital Seminar Tour 2016
Date: April 14 2016
Location: Chelmsford, Massachusetts, USA
Description: In digital standards, every generational change introduces new challenges and risks. In this seminar, we will share our industry expertise and discuss solutions for high-speed digital design and test to help you anticipate these challenges, reduce risks and accelerate your designs. You will learn new design and test strategies for signal integrity, USB 3.1 Tx/Rx test, Type-C Connector, PAM-4/400G, and DDR4/LPDDR4.

Who should attend:
Design engineers, signal integrity engineers, quality engineers, validation engineers, test engineers, architects, project managers, program managers, application managers, and application engineers.

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About the Author

Interference Technology

Established in 1970, Interference Technology helps EMI/EMC engineers find solutions to their various testing, design, application and regulatory issues by publishing articles, news and other practical content. We help suppliers in these areas to find the right customers for their components, materials, test equipment and services through a wide range of marketing services, including lead generation, branding, market research and events. The publication is available in various printed and electronic media formats, with readers in over 60 countries. We also publish issues in local languages in China, Japan and Europe.

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